1. Field of the Invention
The present invention relates to a semiconductor technique for realizing, e.g., a transistor or a multi-layered wiring structure having a size on the order of submicrons and, more particularly, to a semiconductor device using a self-alignment technique and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a large-scale integrated (LSI) circuit formed by integrating a large number of transistors or resistors on a single chip is often used in a main part of a computer or communication equipment. To improve the performance of the LSI is the key to achieving high performance of the entire equipment. For this reason, it is important to improve the performance of a semiconductor device, e.g., a field-effect transistor which constitutes a basic element of the LSI.
In addition, a degree of integration of a memory or logic element has been increased four times every three years, and a design rule has entered a new era of submicrons. Nowadays, mass-production of 4-Mbit dRAMs having a design rule of 0.8 .mu.m and research and development of 0.3- to 0.6-.mu.m rule devices have begun.
In order to form a microelement having a deep submicron size, the following five factors are important.
(1) Lithography technique
(2) Oxidizing technique (element isolating technique)
(3) Diffusing technique (formation of source.cndot.drain of MOSFET, trench side wall, and emitter.cndot.base.cndot.collector of bipolar transistor)
(4) Planarizing technique (metal plug formation, insulating film formation, and flattening)
(5) Wiring processing technique (new material, high-selectivity etching)
The above factors will be described in detail below.
(1) Lithography Technique
When a design rule is a size of about 0.2 .mu.m, a required precision is as very strict as 10 to 20 nm which is close to a physical limit of lithography. For example, when satisfactory alignment margins are kept between contact holes and wiring patterns, a space between adjacent wiring patterns is limited by an interval between the contact holes.
When wiring patterns 41, 43, and 46 are formed with alignment margins with respect to contact holes 42, 44, and 45, respectively, as shown in FIG. 5B, a minimum space between adjacent wiring patterns is narrowed at a portion of the contact hole. As a result, a short-circuit easily occurs due to an etching residue. Moreover, narrowing of the space leads to an increase in interwiring capacitance. In addition, the contact holes 44 and 45 must be formed with alignment margins with respect to an element formation region 40 in consideration of a mask misalignment.
If no misalignment occurs, therefore, the widths of the element formation region, the contact hole, and the wiring can be the same, and so the interwiring space is not locally narrowed to effectively reduce the interwiring capacitance. In addition, a space can be reduced in a region where the interwiring capacitance need not be taken into consideration. As a result, a cell size can be decreased to realize element integration at a higher density. No practical manufacturing method, however, has been proposed so far.
(2) Oxidizing Technique (Element Isolating Technique)
As micropatterning of an element progresses, the width of element isolation must be inevitably decreased. In a conventional LOCOS method, as is well known, an oxide film in an isolation region grows by exudation toward an element, and bird's beaks are formed. That is, regardless of the fact that an element region is covered with a nitride film mask, an oxidizing agent exudes under the mask to progress oxidation although an oxidation rate is decreased.
In order to eliminate this drawback, polycrystalline Si may be interposed between the nitride film and a buffer oxide film, thereby reducing the degree of bird's beaks. Although a demand has arisen for a drastic measure, however, no such measure is present, and an oxidation method called directional oxidation is desired.
(3) Diffusing Technique
A microelement having a submicron size, e.g., a micro field-effect transistor (FET) having a submicron size has a shallow diffusion layer such as a source.cndot.drain region. In this case, a junction depth required for a 0.5-.mu.m generation device is 0.15 to 0.2 .mu.m, and that required for a 0.2-.mu.m generation device is 0.1 .mu.m or less. That is, a diffusing technique with higher precision is required.
As a method of forming a shallow diffusion layer, a low-acceleration ion-implantation method has been conventionally widely used, and an impurity solid-phase diffusion method is recently used. By this solid-phase diffusion method, a shallow source.cndot.drain region having a thickness of about 0.1 .mu.m can be formed, and a depth of about 0.1 .mu.m can be realized for an n.sup.+ -p junction. In addition, by using a method in which ion implantation of Si.sup.+, Ge.sup.+, and Sn.sup.+ is performed to form a surface layer of an Si single crystal layer into an amorphous layer and then low-acceleration BF.sub.2 ion implantation is performed, a depth of about 0.1 .mu.m can be achieved for a p.sup.+ -n junction even after annealing for activation is performed.
The resistance of a diffusion layer having a thickness of 0.1 .mu.m, however, is as high as a sheet resistance of 100 .OMEGA./.quadrature. or more. In order to increase an operation speed of a semiconductor device, therefore, the surface of a diffusion region must be metallized to decrease its resistance. For this reason, a selective silicification method, so-called self-aligned silicide has been examined in recent years.
A conventional example in which a self-aligned silicide is formed on a shallow p-n junction having a depth of 0.2 .mu.m or less will be described below with reference to FIGS. 1A to 1E. Referring to FIG. 1A, a field oxide film 1a and a gate insulating film 2 are formed by thermal oxidation on an Si substrate 1 having (100) crystal orientation, gate electrodes 3a and 3b, an insulating film cap 4, and a side-wall insulating film 5 are formed, and a metal film 6 consisting of Ti or Co is deposited on the entire surface of the substrate. Subsequently, a silicide layer 7 is formed on only Si by lamp annealing, and a non-reacted metal film is removed by etching, thereby selectively leaving the silicide layer 7 on only Si, as shown in FIG. 1B. Subsequently, an impurity 8 having a conductivity type different from that of the substrate 1 is ion-implanted, as shown in FIG. 1C, and a diffusion region 9 is formed under the silicide layer 7, as shown in FIG. 1D. According to this method, by forming the silicide layer 7 having a thickness of, e.g., 50 nm, a sheet resistance can be reduced to be 3 to 5 .OMEGA./.quadrature..
This method, however, has the following problems. That is, if a natural oxide film or a surface contamination layer formed by dry etching is present on the Si surface, it is difficult to perform a uniform reaction between a metal and Si, and a nonuniform boundary structure is formed an interface. In this case, electric field concentration locally occurs to increase a p-n junction leakage current, and a p-n junction may be destroyed accordingly. For this reason, it is very difficult to form a p-n junction having a depth of 0.1 .mu.m or less with this method. In addition, a total thickness of 0.1 .mu.m or less is required for a micro transistor having a design rule of 0.3 .mu.m or less. For this reason, the total thickness must be decreased to form a diffusion layer having a thickness of several tens nm. When the thickness of a silicide film is decreased, a resistance of a source.cndot.drain is increased, and p-n junction characteristics are degraded if the thickness of a diffusion layer becomes 50 nm or less. The reasons for this junction degradation are as follows. That is, a GR center caused by metal diffusion from a metal compound adversely affects the junction characteristics and enters into a diffusion layer thickness region at which a junction leakage current starts increasing. Also, since the shape of a diffusion layer reflects projections and recesses on the silicide/Si interface when the thickness of the diffusion layer is decreased, electric field concentration easily occurs.
In order to prevent the erosion on the Si substrate upon silicide formation as described above, after an Si film is selectively grown on a source.cndot.drain to increase the Si thickness, a normal silicide process may be performed. Since doping cannot be perfectly performed depending on the thickness of selectively grown Si, however, a source.cndot.drain impurity diffusion layer does not reach the original substrate surface and therefore cannot serve as a source.cndot.drain. In order to form a shallow junction having a depth of 0.1 .mu.m or less, therefore, it is required to form a metal silicide which does not erode the Si substrate and has a low resistance and to form a high-concentration impurity diffusion layer therebelow.
(4) Planarizing Technique
In order to form a multilayered wiring structure, a technique of forming plugs for plugging contact holes or via holes and a technique of forming an SiO.sub.2 film having a high step coverage are required because projections and recesses are increased upon stacking wiring layers. In addition, a wiring layer having a low resistance and high reliability must be used.
Current problems of an insulating film formation technique as one important technique of multilayered wiring techniques will be described below. As a method of forming an interlayer insulating film, plasma TEOS-CVD is recently generally used since it has a step coverage higher than that of SiH.sub.4 -based plasma CVD. When an aspect ratio of an interwiring is 1 or more, however, a deposited shape includes spaces because the step coverage is not 100%. The cause of the low step coverage is as follows. That is, since a reaction gas and a production gas cannot be satisfactorily exchanged in the space portions, the concentration of the reaction gas in a recess portion is reduced as compared with that in a flat portion or a projecting portion. As a result, an SiO.sub.2 growth rate is determined not by a reaction rate on the surface but by a reaction gas supply or diffusion rate.
In order to improve the step coverage or the surface shape of the plasma TEOS film, ozone may be added or a temperature range of 300.degree. C. to 350.degree. C. may be selected. These techniques, however, cannot be drastic measures. Therefore, a new oxide film deposition method is required for a device in a deep submicron region.
(5) Wiring Processing Technique
Of the multilayered wiring techniques, various types of metal wiring pattern formation techniques are predicted to have problems in the future. In W wiring processing, for example, it is difficult to perform high-selectivity etching on a gate oxide film. This is because no satisfactory etching rate cannot be obtained by a Cl.sub.2 -based etching which facilitates high-selectivity etching with SiO.sub.2 since a vapor pressure of WCl.sub.6 is low. As a result, the selectivity with SiO.sub.2 is reduced to be at most 7 to 8. In processing in which 200-nm thick W is to be etched on 5-nm thick SiO.sub.2, therefore, if 30% over etching with respect to just etching is performed, the 5-nm thick SiO.sub.2 film on a source.cndot.drain is completely removed by etching, and the underlying Si substrate is also etched. When an F-based gas such as SF.sub.6 gas is used, although high-rate etching can be performed since a vapor pressure of WF.sub.6 as a fluoride of W is very high, it is difficult to increase the selectivity with respect to SiO.sub.2 to be 7 or more. Therefore, it is very difficult to form a micro wiring pattern of W.
It is far more difficult to perform etching for Cu (1.68 .mu..OMEGA..multidot.cm) having a lower resistance than that of Al (2.5 to 3 .mu..OMEGA..multidot.cm). For example, even Cu chloride having a highest vapor pressure does not evaporate until a temperature is heated up to about 300.degree. C. to 350.degree. C. This high-temperature etching brings about the following two problems. First, since only few Cu etching masks can withstand such a high-temperature Cl.sub.2 (BCl.sub.3) atmosphere, a new mask must be developed. Second, if a low-temperature portion is exposed in an etching chamber, Cu chloride evaporated from a wafer is condensed to serve as a generation source of particles. Therefore, a metal wiring pattern formation technique requiring no metal patterning must be developed.
As described above, as long as the conventional process techniques are adopted, it is very difficult to form various types of patterns free from exudation such as an element isolation region, e.g., a series of micropatterns such as a shallow p-n junction region, a silicided region of a source-drain, metal and metal/polySi gates, low-resistance wiring, and multilayered wiring. In addition, in order to form a pattern free from exudation, a mask alignment precision beyond a physical limit is required in lithography. If high-precision processing is required in etching, therefore, a degree of freedom of selection for materials is significantly decreased.